Reducing energy consumption when applying body bias to substrate having sets of NAND strings

ABSTRACT

Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of U.S. patent applicationSer. No. 12/759,581, filed Apr. 13, 2010 (published on Aug. 5, 2010 asUS2010/0195398 and issued on Aug. 16, 2011 as U.S. Pat. No. 8,000,146),which in turn is a divisional application of U.S. patent applicationSer. No. 12/335,803, filed Dec. 16, 2008 (issued on Jul. 6, 2010 as U.S.Pat. No. 7,751,244), which in turn is a divisional application of U.S.patent application Ser. No. 11/618,791, filed Dec. 30, 2006 (issued onDec. 23, 2008 as U.S. Pat. No. 7,468,920), both of which areincorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to non-volatile memory.

2. Description of the Related Art

Semiconductor memory has become increasingly popular for use in variouselectronic devices. For example, non-volatile semiconductor memory isused in cellular telephones, digital cameras, personal digitalassistants, mobile computing devices, non-mobile computing devices andother devices. Electrically Erasable Programmable Read Only Memory(EEPROM) and flash memory are among the most popular non-volatilesemiconductor memories. With flash memory, also a type of EEPROM, thecontents of the whole memory array, or of a portion of the memory, canbe erased in one step, in contrast to the traditional, full-featuredEEPROM.

Both the traditional EEPROM and the flash memory utilize a floating gatethat is positioned above and insulated from a channel region in asemiconductor substrate. The floating gate is positioned between thesource and drain regions. A control gate is provided over and insulatedfrom the floating gate. The threshold voltage (V_(TH)) of the transistorthus formed is controlled by the amount of charge that is retained onthe floating gate. That is, the minimum amount of voltage that must beapplied to the control gate before the transistor is turned on to permitconduction between its source and drain is controlled by the level ofcharge on the floating gate.

Some EEPROM and flash memory devices have a floating gate that is usedto store two ranges of charges and, therefore, the memory element can beprogrammed/erased between two states, e.g., an erased state and aprogrammed state. Such a flash memory device is sometimes referred to asa binary flash memory device because each memory element can store onebit of data.

A multi-state (also called multi-level) flash memory device isimplemented by identifying multiple distinct allowed/valid programmedthreshold voltage ranges. Each distinct threshold voltage rangecorresponds to a predetermined value for the set of data bits encoded inthe memory device. For example, each memory element can store two bitsof data when the element can be placed in one of four discrete chargebands corresponding to four distinct threshold voltage ranges.

Typically, a program voltage V_(PGM) applied to the control gate duringa program operation is applied as a series of pulses that increase inmagnitude over time. In one possible approach, the magnitude of thepulses is increased with each successive pulse by a predetermined stepsize, e.g., 0.2-0.4 V. V_(PGM) can be applied to the control gates offlash memory elements. In the periods between the program pulses, verifyoperations are carried out. That is, the programming level of eachelement of a group of elements being programmed in parallel is readbetween successive programming pulses to determine whether it is equalto or greater than a verify level to which the element is beingprogrammed. For arrays of multi-state flash memory elements, averification step may be performed for each state of an element todetermine whether the element has reached its data-associated verifylevel. For example, a multi-state memory element capable of storing datain four states may need to perform verify operations for three comparepoints.

Moreover, when programming an EEPROM or flash memory device, such as aNAND flash memory device in a NAND string, typically V_(PGM) is appliedto the control gate and the bit line is grounded, causing electrons fromthe channel of a cell or memory element, e.g., storage element, to beinjected into the floating gate. When electrons accumulate in thefloating gate, the floating gate becomes negatively charged and thethreshold voltage of the memory element is raised so that the memoryelement is considered to be in a programmed state. More informationabout such programming can be found in U.S. Pat. No. 6,859,397, titled“Source Side Self Boosting Technique For Non-Volatile Memory,” and inU.S. Patent Application Publication 2005/0024939, titled “Detecting OverProgrammed Memory,” published Feb. 3, 2005 (issued as U.S. Pat. No.6,917,542 on Jul. 12, 2005); each of which is incorporated herein byreference in their entirety.

However, techniques for optimizing performance of a non-volatile storagesystem are needed.

SUMMARY OF THE INVENTION

The present invention addresses the above and other issues by providinga method for operating non-volatile storage in which a body bias isapplied to optimize performance.

In one embodiment, a method for operating non-volatile storage includesreading non-volatile storage elements in at least one set ofnon-volatile storage elements while biasing a substrate at a first biaslevel, where the at least one set of non-volatile storage elements isformed, at least in part, on the substrate. Based on the reading, afirst error metric is determined. If the first error metric exceeds athreshold, a second bias level is determined for biasing the substratewhen performing a subsequent read of non-volatile storage elements inthe at least one set of non-volatile storage elements. The first errormetric can include a count of bit errors.

The method can further include reading non-volatile storage elements inthe at least one set of non-volatile storage elements while biasing thesubstrate at the second bias level, and determining a second errormetric, based on the reading while biasing the substrate at the secondbias level. If the second error metric exceeds the threshold, a thirdbias level is determined for biasing the substrate when performing asubsequent read of non-volatile storage elements in the at least one setof non-volatile storage elements. When the second bias level is lowerthan the first bias level, the third bias level can be higher than thefirst bias level if the second error metric indicates more errors thanthe first error metric. When the second bias level is higher than thefirst bias level, the third bias level can be lower than the first biaslevel if the second error metric indicates more errors than the firsterror metric.

In one approach, if the first error metric does not exceed thethreshold, the substrate is biased at the first bias level whenperforming a subsequent read of non-volatile storage elements in the atleast one set of non-volatile storage elements.

The first error metric can be determined based on reading non-volatilestorage elements in a number of sets of non-volatile storage elementswhich are formed, at least in part, on the substrate, where the firsterror metric is determined based on error metrics which are determinedfor each of the sets. In another approach, the first error metric isdetermined based on multiple read operations performed on non-volatilestorage elements in the at least one set of non-volatile storageelements. The at least one set of non-volatile storage elements can beprovided in at least one NAND string which is formed, at least in part,on the substrate.

In one approach, the biasing includes applying a voltage based on thefirst bias level to the substrate. In another approach, the biasing caninclude applying a first voltage to the substrate, and increasing thevoltage to the source, drain and gate of the set of non-volatile storageelements by a second voltage, where a difference between the first andsecond voltages is based on the first bias level.

The first error metric can be for a page of data stored by the at leastone set of non-volatile storage elements.

In another embodiment, a method for operating non-volatile storageincluded tracking programming cycles experienced by at least one set ofnon-volatile storage elements which is formed, at least in part, on asubstrate, and biasing the substrate at a bias level during operationsperformed on the at least one set of non-volatile storage elements,where the bias level is based on the tracking For example, theoperations can include programming, reading and/or verifying.

In one approach, the bias level increases as a number of the programmingcycles increases. In another approach, the bias level decreases as anumber of programming cycles increases.

The tracking can include separately tracking programming cyclesexperienced by different sets of non-volatile storage elements which areformed, at least in part, on different portions of the substrate. Inthis case, an aggregate usage metric is determined based on the separatetracking, and the bias level is based on the aggregate usage metric.

In another approach, the tracking includes separately trackingprogramming cycles experienced by different sets of non-volatile storageelements which are formed, at least in part, on different portions ofthe substrate. In this case, the biasing includes biasing the differentportions of the substrate at different bias levels during operationsperformed on the different sets of non-volatile storage elements, wherethe different bias levels are based on the tracking

In another embodiment, a method for operating non-volatile storageincludes performing operations on non-volatile storage elements indifferent sets of non-volatile storage elements, where the differentsets of non-volatile storage elements are formed, at least in part, ondifferent portions of a substrate. The different portions of thesubstrate are biased separately while the operations are performed onthe non-volatile storage elements therein.

Data can be read from a memory which indicates respective bias levelsfor each of the different portions of the substrate, in which case thebiasing is responsive to the reading.

The different sets of non-volatile storage elements can be in differentplanes of a chip, where each plane includes a number of blocks, and eachblock is erasable as a unit. The different sets of non-volatile storageelements can be in different blocks, where each block is erasable as aunit. The different sets of non-volatile storage elements can be indifferent pages, where each page is programmed as a unit.

At least two different portions of the substrate can be biased atdifferent bias levels. Also, the different portions of the substrate canbe biased concurrently.

In another embodiment, a method for operating non-volatile storageincludes performing operations on, and biasing, a first set of NANDstrings during a first time interval, where the biasing includesincreasing the source, drain and gate voltages provided to the NANDstring by a first voltage and providing a second voltage to a p-wellregion on which the first set of NAND strings are formed, at least inpart. A difference between the first and second voltages can be based ona desired bias level. The method further includes floating, or providinga fixed voltage to, a source side of a second set of NAND strings whichare formed, at least in part, on the p-well region. A level of the fixedvoltage can be set based on the desired bias level. Operations are notperformed on the second set of NAND strings during the first timeinterval. The first voltage can be provided via a first source voltagesupply line.

In one approach, the floating of the source side of the second set ofNAND strings includes floating a second source voltage supply line forthe second set of NAND strings. Or, the providing the fixed voltage tothe source side of the second set of NAND strings includes providing thefixed voltage to the second source voltage supply line for the secondset of NAND strings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top view of a NAND string.

FIG. 2 is an equivalent circuit diagram of the NAND string of FIG. 1.

FIG. 3 is a block diagram of an array of NAND flash storage elements.

FIG. 4 depicts a cross-sectional view of a NAND string formed on asubstrate.

FIGS. 5a-5h depict behavior of memory device parameters versustemperature and body bias level.

FIG. 6 depicts a control curve of body bias level versus temperature.

FIG. 7 depicts a process for setting a body bias level based ontemperature, accounting for different temperature-dependent effects.

FIG. 8a-8c depict processes for operating non-volatile storage in whicha body bias is applied.

FIG. 9a depicts voltages applied to a set of word lines during a programoperation.

FIG. 9b depicts voltages applied to a set of word lines during a read orverify operation.

FIG. 10a depicts a threshold voltage as a function of word lineposition.

FIGS. 10b-10d depict example control curves of body bias as a functionof word line position.

FIG. 10e depicts a process for operating non-volatile storage in whichbody bias is varied based on selected word line position.

FIG. 11 depicts a process for operating non-volatile storage in whichbody bias is varied based on an error metric.

FIG. 12a depicts a control curve of body bias as a function of a numberof programming cycles.

FIG. 12b depicts a process for operating non-volatile storage in whichbody bias is varied based on a number of programming cycles.

FIG. 13a depicts non-volatile storage in which planes and blocks of achip have a common body bias.

FIG. 13b depicts non-volatile storage in which planes of a chip haveseparate body biases.

FIG. 14a depicts non-volatile storage in which a body bias is appliedfor storage elements associated with an even page.

FIG. 14b depicts non-volatile storage in which a body bias is appliedfor storage elements associated with an odd page.

FIG. 15 depicts a process for operating non-volatile storage in whichseparate body biases are applied at the chip, plane, block and/or pagelevel.

FIG. 16 depicts an example of an array of storage elements, includingdifferent sets of NAND strings.

FIG. 17 depicts a process for operating non-volatile storage in whichdifferent body biases are applied to different sets of NAND strings.

FIG. 18 depicts a process for setting a body bias level based onmultiple factors.

FIG. 19 is a block diagram of a non-volatile memory system using singlerow/column decoders and read/write circuits.

FIG. 20 is a block diagram of a non-volatile memory system using dualrow/column decoders and read/write circuits.

FIG. 21 is a block diagram depicting one embodiment of a sense block.

FIG. 22 depicts an example of an organization of a memory array intoblocks for odd-even and all bit line memory architectures.

FIG. 23 depicts an example set of threshold voltage distributions.

FIG. 24 depicts an example of a two-pass technique of programming amulti-state storage element that stores data for two different pages: alower page and an upper page.

FIGS. 25a-c show various threshold voltage distributions and describe aprocess for programming non-volatile memory.

FIG. 26 is a flow chart describing one embodiment of a method forprogramming non-volatile memory.

FIG. 27 depicts an example pulse train applied to the control gates ofnon-volatile storage elements during programming.

DETAILED DESCRIPTION

The present invention provides a method for operating non-volatilestorage in which a body bias is applied to optimize performance.

One example of a memory system suitable for implementing the presentinvention uses the NAND flash memory structure, which includes arrangingmultiple transistors in series between two select gates. The transistorsin series and the select gates are referred to as a NAND string. FIG. 1is a top view showing one NAND string. FIG. 2 is an equivalent circuitthereof. The NAND string depicted in FIGS. 1 and 2 includes fourtransistors, 100, 102, 104 and 106, in series and sandwiched between afirst select gate 120 and a second select gate 122. Select gate 120gates the NAND string connection to bit line 126. Select gate 122 gatesthe NAND string connection to source line 128. Select gate 120 iscontrolled by applying the appropriate voltages to control gate 120CG.Select gate 122 is controlled by applying the appropriate voltages tocontrol gate 122CG. Each of the transistors 100, 102, 104 and 106 has acontrol gate and a floating gate. Transistor 100 has control gate 100CGand floating gate 100FG. Transistor 102 includes control gate 102CG andfloating gate 102FG. Transistor 104 includes control gate 104CG andfloating gate 104FG. Transistor 106 includes a control gate 106CG andfloating gate 106FG. Control gate 100CG is connected to word line WL3,control gate 102CG is connected to word line WL2, control gate 104CG isconnected to word line WL1, and control gate 106CG is connected to wordline WL0. The control gates can also be provided as portions of the wordlines. In one embodiment, transistors 100, 102, 104 and 106 are eachstorage elements, also referred to as memory cells. In otherembodiments, the storage elements may include multiple transistors ormay be different than that depicted in FIGS. 1 and 2. Select gate 120 isconnected to select line SGD (drain select gate). Select gate 122 isconnected to select line SGS (source select gate).

FIG. 3 is a circuit diagram depicting three NAND strings. A typicalarchitecture for a flash memory system using a NAND structure willinclude several NAND strings. For example, three NAND strings 320, 340and 360 are shown in a memory array having many more NAND strings. Eachof the NAND strings includes two select gates and four storage elements.While four storage elements are illustrated for simplicity, modern NANDstrings can have up to thirty-two or sixty-four storage elements, forinstance.

For example, NAND string 320 includes select gates 322 and 327, andstorage elements 323-326, NAND string 340 includes select gates 342 and347, and storage elements 343-346, NAND string 360 includes select gates362 and 367, and storage elements 363-366. Each NAND string is connectedto the source line by its select gates (e.g., select gates 327, 347 or367). A selection line SGS is used to control the source side selectgates. The various NAND strings 320, 340 and 360 are connected torespective bit lines 321, 341 and 361, by select transistors in theselect gates 322, 342, 362, etc. These select transistors are controlledby a drain select line SGD. In other embodiments, the select lines donot necessarily need to be in common among the NAND strings; that is,different select lines can be provided for different NAND strings. Wordline WL3 is connected to the control gates for storage elements 323, 343and 363. Word line WL2 is connected to the control gates for storageelements 324, 344 and 364. Word line WL1 is connected to the controlgates for storage elements 325, 345 and 365. Word line WL0 is connectedto the control gates for storage elements 326, 346 and 366. As can beseen, each bit line and the respective NAND string comprise the columnsof the array or set of storage elements. The word lines (WL3, WL2, WL1and WL0) comprise the rows of the array or set. Each word line connectsthe control gates of each storage element in the row. Or, the controlgates may be provided by the word lines themselves. For example, wordline WL2 provides the control gates for storage elements 324, 344 and364. In practice, there can be thousands of storage elements on a wordline.

Each storage element can store data. For example, when storing one bitof digital data, the range of possible threshold voltages (V_(TH)) ofthe storage element is divided into two ranges which are assignedlogical data “1” and “0.” In one example of a NAND type flash memory,the V_(TH) is negative after the storage element is erased, and definedas logic “1.” The V_(TH) after a program operation is positive anddefined as logic “0.” When the V_(TH) is negative and a read isattempted, the storage element will turn on to indicate logic “1” isbeing stored. When the V_(TH) is positive and a read operation isattempted, the storage element will not turn on, which indicates thatlogic “0” is stored. A storage element can also store multiple levels ofinformation, for example, multiple bits of digital data. In this case,the range of V_(TH) value is divided into the number of levels of data.For example, if four levels of information are stored, there will befour V_(TH) ranges assigned to the data values “11”, “10”, “01”, and“00.” In one example of a NAND type memory, the V_(TH) after an eraseoperation is negative and defined as “11”. Positive V_(TH) values areused for the states of “10”, “01”, and “00.” The specific relationshipbetween the data programmed into the storage element and the thresholdvoltage ranges of the element depends upon the data encoding schemeadopted for the storage elements. For example, U.S. Pat. No. 6,222,762and U.S. Patent Application Pub. 2004/0255090, both of which areincorporated herein by reference in their entirety, describe variousdata encoding schemes for multi-state flash storage elements.

Relevant examples of NAND type flash memories and their operation areprovided in U.S. Pat. Nos. 5,386,422, 5,570,315, 5,774,397, 6,046,935,6,456,528 and 6,522,580, each of which is incorporated herein byreference.

When programming a flash storage element, a program voltage is appliedto the control gate of the storage element and the bit line associatedwith the storage element is grounded. Electrons from the channel areinjected into the floating gate. When electrons accumulate in thefloating gate, the floating gate becomes negatively charged and theV_(TH) of the storage element is raised. To apply the program voltage tothe control gate of the storage element being programmed, that programvoltage is applied on the appropriate word line. As discussed above, onestorage element in each of the NAND strings share the same word line.For example, when programming storage element 324 of FIG. 3, the programvoltage will also be applied to the control gates of storage elements344 and 364.

FIG. 4 depicts a cross-sectional view of an NAND string formed on asubstrate. The view is simplified and not to scale. The NAND string 400includes a source-side select gate 406, a drain-side select gate 424,and eight storage elements 408, 410, 412, 414, 416, 418, 420 and 422,formed on a substrate 490. A number of source/drain regions, one exampleof which is source drain/region 430, are provided on either side of eachstorage element and the select gates 406 and 424. In one approach, thesubstrate 490 employs a triple-well technology which includes a p-wellregion 492 within an n-well region 494, which in turn is within a p-typesubstrate region 496. The NAND string and its non-volatile storageelements can be formed, at least in part, on the p-well region. A sourcesupply line 404 with a potential of V_(SOURCE) is provided in additionto a bit line 426 with a potential of V_(BIT LINE). In one possibleapproach, a body bias voltage, V_(B), is applied to the p-well region492 via a terminal 402. A voltage can also be applied to the n-wellregion 494 via a terminal 403. In one approach, a bias is applied to thenon-volatile storage elements by applying V_(B) to the p-well regionwhile grounding the n-well region (0 V). In another approach, a bias isapplied to the non-volatile storage elements by applying V_(B) to boththe p-well region and the n-well region.

During programming, V_(PGM) is provided on a selected word line, in thisexample, WL4, which is associated with storage element 416. Further,recall that the control gate of a storage element may be provided as aportion of the word line. For example, WL0, WL1, WL2, WL3, WL4, WL5, WL6and WL7 can extend via the control gates of storage elements 408, 410,412, 414, 416, 418, 420 and 422, respectively. A pass voltage, V_(PASS)is applied to the remaining word lines associated with NAND string 400,in one possible boosting scheme. V_(SGS) and V_(SGD) are applied to theselect gates 406 and 424, respectively.

FIGS. 5a-5h depict behavior of memory device parameters versustemperature and body bias level. In non-volatile storage devices, suchas NAND flash memory devices, temperature variations present variousissues, e.g., in reading and writing data. A memory device is subject tovarying temperatures based on the environment in which it is located.For example, some current memory devices are rated for use between −40°C. and +85° C. Temperature affects many transistor parameters, thedominant among which is the threshold voltage. As temperature rises, thethreshold voltage (V_(TH)) drops by approximately 2 mV/° C., as depictedin FIG. 5a. ΔV_(TH)/ΔTemp. is one measure of a temperature coefficient.The temperature coefficient depends on various characteristics of thememory device, such as doping, oxide thickness and so forth. Moreover,the temperature coefficient is expected to increase in magnitude asmemory dimensions are reduced.

Temperature variations can cause read errors and widen the thresholdvoltage distributions. One technique for compensating for temperaturevariations involves changing the read/verify voltages applied to aselected word line in a way which accounts for the temperature variationof a selected storage element's threshold voltage. However, thistechnique by itself is not efficient enough to prevent V_(TH)distributions and margins between states from widening as temperaturevaries. Ideally, if one could fully compensate for temperature changesof all memory device parameters, that is, make all memory deviceparameters remain the same even though temperature changes, V_(TH)distributions and margins would be the same at different temperatures.However, with existing compensation techniques, other memory deviceparameters are not compensated. For example, in addition to V_(TH),other memory device parameters showing temperature sensitivity includesub-V_(TH) slope (referred to as sub-threshold slope) and depletionlayer width. Variations in these parameters also result in wideningV_(TH) distributions due to temperature changes. Further, although readand verify voltages can be changed with temperature, read voltages(V_(READ)) and/or select gate voltages (V_(SGS) and V_(SGD)) are nottypically varied with temperature.

To address these issues, temperature compensation can be provided byapplying a temperature-dependent body bias to the memory device. It hasbeen observed that V_(TH) decreases as bias voltage, V_(BS), increases,as depicted in FIG. 5b. V_(BS) denotes a difference between a biasvoltage, V_(B), applied to the p-well of the memory device and avoltage, V_(S), at the source side of a storage element. Note that apositive bias, referred to as a forward body bias (FBB), or a negativebias, referred to a reverse body bias (RBB), can be applied.

Sub-V_(TH) slope is a measure of how difficult it is to sense the V_(TH)of a storage element. In particular, sub-V_(TH) slope=d(log₁₀I_(D))/dV_(CG), where I_(D) is the drain current of a storageelement and V_(CG) is the control gate voltage. A lower sub-V_(TH) slopeis better for good sensing. Sub-V_(TH) slope increases with temperature,as depicted in FIG. 5c. Further, FIG. 5d indicates that a lower V_(BS)results in a lower sub-V_(TH) slope. Thus, applying a lower V_(BS) athigher temperatures to compensate for V_(TH) can also partiallycompensate for the increase in sub-V_(TH) slope. Further, depletionlayer width is reduced as temperature increases, as depicted in FIG. 5e.Moreover, the depletion layer width drops as V_(BS) increases, asdepicted in FIG. 5f. Thus, applying a lower V_(BS) at highertemperatures can partially compensate for the reduced depletion layerwidth at the higher temperatures. 1/f noise decreases as temperatureincreases, as depicted in FIG. 5g, and as V_(BS) decreases, as depictedin FIG. 5h. Thus, the higher 1/f noise at lower temperatures can bepartially compensated by a higher V_(BS).

In particular, 1/f noise is produced in NAND storage elements due totraps in the tunnel oxide. This problem becomes worse with scaling.Experiments indicate that 1/f noise can be reduced in NAND arrays usingforward body bias (FBB), in which V_(BS)>0 V. FBB can be used in variousways with reverse body bias (RBB), in which V_(BS)<0 V, in non-volatilestorage systems. Further, while FBB does reduce 1/f noise, it candegrade sub-V_(TH) slope. An option to gain the advantages of both FBBand RBB is to use FBB at lower temperatures when 1/f noise is high, anduse zero bias or RBB at higher temperatures where sub-threshold slopedegradation is more of an issue. Further, both the device doping andbody bias value can be optimally chosen to gain benefits.

In one approach, for a FBB implementation, the body bias is applied tothe p-well in which the storage elements are formed. The n-well can alsobe charged to the same voltage to minimize the forward current throughthe p-n junction formed between the two wells. The p-type substrateregion can be grounded, in which case the p-n junction formed betweenthe p-type region and the n-well is reverse biased when FBB is appliedto a NAND array, for instance. RBB can be implemented in a NAND array bychanging the potentials of the source, gate and drain while keeping thebody grounded. In another approach, RBB is implemented by changing thebody potential. For example, to change the body-to-source voltage(V_(BS)) from −0.5 V to −1 V, the source, gate, drain and bodypotentials initially can be chosen as 1 V, 5 V, 0.7 V and 0.5 V,respectively. These values are then changed to 1 V, 5 V, 0.7 V and 0 V,respectively. Specifically, in the first case,V_(BS)=V_(B)−V_(S)=0.5−1=−0.5 V and, in the second case,V_(BS)=V_(B)−V_(S)=0−1=−1 V.

FIG. 6 depicts a control curve of body bias level versus temperature. Asmentioned above, reducing V_(BS) as temperature increases can compensatefor changes in V_(TH) and other device parameters, thereby flatteningthe curves of FIGS. 5a, 5c, 5e and 5g. This approach improves upon othertechniques in which only V_(TH) is compensated. Further, the advantagesachieved using the techniques disclosed herein are in contrast tocompensation techniques used in high power logic devices. Such devicescan regulate their temperature and therefore need not compensate fortemperature variations. Moreover, compensation techniques used in highpower logic devices do not account for the particular issues relating tonon-volatile storage devices.

For instance, the compensation of sub-V_(TH) slope enables uniformattenuation of sensing uncertainties across all temperature ranges.Further, 1/f noise is becoming a serious concern in NAND flash memoriesas well. The compensation of 1/f noise, which increases at lowertemperatures, is a further benefit for non-volatile storage devices. Thecontrol curve of FIG. 6, which can represent a linear or non-linearfunction, can be implemented in different ways. In one approach, V_(BS)is set based on a temperature-dependent reference signal. In an exampleimplementation, ΔV_(BS)/ΔTemp. is approximately −4 mV/° C. so that achange in V_(BS) of 0.4 mV results over a temperature range of 100° C.In this example, V_(BS) may be 0.4 mV at −15° C. and 0 V at 85° C. Or,V_(BS) can be set to 0 V at room temperature or other selectedtemperature. Generally, the optimal control curve for a particularnon-volatile storage device can be determined based on test resultsand/or theoretical results which identify the temperature-varyingbehavior of the compensated parameters. In some cases, different bodybias levels would result from consideration of different parametersalone, in which case an optimization can be performed to arrive at anoptimal control curve. For example, an average of the different bodybias levels can be taken to arrive at the optimal control curve. Or, thedifferent body bias levels can be weighted based on the relativeimportance of the parameter on which they are based. In this way, thecontrol curve can be optimized and customized.

FIG. 7 depicts a process for setting a body bias level based ontemperature, accounting for different temperature-dependent effects. Atemperature-dependent reference signal is provided to a body bias leveldetermination process 710, which outputs a body bias level which is setto vary with temperature to compensate at least one temperature-varyingcharacteristic of a set of non-volatile storage elements, including athreshold voltage 712, sub-V_(TH) slope 714, depletion layer width 716and noise 718.

Various techniques are known for providing a temperature-dependentreference signal. In one possible approach, a band gap circuit is used.For example, U.S. Pat. No. 6,801,454, titled “Voltage GenerationCircuitry Having Temperature Compensation,” incorporated herein byreference, describes a voltage generation circuit which outputs readvoltages to a non-volatile memory based on a temperature coefficient.The circuit uses a band gap current which includes atemperature-independent portion and a temperature-dependent portionwhich increases as temperature increases. U.S. Pat. No. 6,560,152,titled “Non-Volatile Memory With Temperature-Compensated Data Read,”incorporated herein by reference, uses a bias generator circuit whichbiases a voltage which is applied to a source or drain of a data storageelement. U.S. Pat. No. 5,172,338, titled “Multi-State EEPROM Read andWrite Circuits and Techniques”, incorporated herein by reference,describes a temperature-compensation technique which uses referencestorage cells that are formed in the same manner, and on the sameintegrated circuit chip, as data storage cells. The reference storagecells provide reference levels against which measured currents orvoltages of the selected cells are compared. Temperature compensation isprovided since the reference levels are affected by temperature in thesame manner as the values read from the data storage cells. Any of thesetechniques, as well as any other known techniques, can be used toprovide a temperature-dependent body bias.

FIG. 8a-8c depict processes for operating non-volatile storage in whicha body bias is applied. Note that in this and other flowcharts providedherein, the steps indicated are not necessarily discrete steps which areperformed separately and are not necessarily performed in the ordershown. In one approach, depicted in FIG. 8a, the body bias applied to aNAND flash array during verify and read operations (or program, verifyand read operations) is designed to be a function of temperature. Forexample, as mentioned, a higher value of V_(BS) can be applied to a NANDarray at lower temperatures than at higher temperatures. Thiscompensates for temperature-dependent changes in the V_(TH) of storageelements of the array, and also partially compensates fortemperature-dependent variations in sub-threshold slope, depletionregion width and “grey zone” margin. When the body is given a positivevoltage with respect to the source and drain regions, the p-n junctiondiodes of the storage elements will conduct a forward bias current if asufficiently high bias voltage is applied, e.g., V_(BS)>0.6 V at roomtemperature. At lower temperatures, the forward bias current is reduced,so applying a body voltage of approximately 0.4 V at −25° C., forinstance, will not cause a high forward bias current.

Moreover, a particular value of body bias can be applied during program,verify and read operations or just during verify and read operations. Ifthe body bias is applied only during verify and read operations and thebody is grounded during programming, the body is charged and dischargedduring every program/verify cycle. While this approach is feasible, itconsumes additional time and power. Maintaining the body bias duringprogram, verify and read operations avoids these drawbacks. For example,a body bias can be set during initial boot up of the memory device.

As an illustration, FIG. 8a-8c depict processes in which a body biaslevel is set for an individual program, read or verify operation. Asmentioned, the body bias level need not be set and applied for eachoperation but can be maintained at a relatively steady level. This levelcan be adjusted periodically to account for changes in temperature, forinstance.

In particular, in the process of FIG. 8a, step 800 includes beginning aprogram, read or verify operation. Step 805 includes receiving atemperature-dependent reference signal. Step 810 includes setting a bodybias level, and step 815 includes applying the bias. For example, thiscan involve applying a temperature-dependent voltage to the p-well andn-well of the substrate (step 820), applying the temperature-dependentvoltage to the p-well while grounding the n-well (step 825) or groundingthe body and applying the temperature-dependent voltage to the sourceand/or drain side of the set of storage elements (step 830). In steps820 and 825, a temperature-dependent voltage (V_(B)) is applied to thesubstrate, where a level of the temperature-dependent voltage is basedon the desired body bias level.

In step 830, a temperature-independent voltage, such as 0 V (groundvoltage), is applied to the substrate, and a temperature-dependentvoltage is applied to the source and/or drain side of the set ofnon-volatile storage elements such as in a block. For instance, thetemperature-independent voltage can be applied concurrently to thep-well region of the substrate and to the n-well region of the substrate(or the n-well region can be grounded), where the set of non-volatilestorage elements are formed, at least in part, on the p-well region, thep-well region is provided in the n-well region, and the n-well region isprovided in a p-type substrate region. Further, a difference between thetemperature-independent voltage and the temperature-dependent voltagecan correspond to the desired bias level. Also, the biasing can involvea forward body bias or reverse body bias. At step 835,temperature-independent word line voltages are set, in one possibleapproach (see FIGS. 9a and 9b). At step 840, the program, read or verifyoperation is performed and, at step 845, the operation ends.

FIG. 8b depicts a process in which a body bias is applied via atemperature-dependent voltage to the p-well and n-well (step 850), or tothe p-well while grounding the n-well (step 852), while atemperature-independent voltage is applied to the source and/or drainside of the set of storage elements (step 854). Steps 800-815 are thesame as discussed previously. Further, at step 856,temperature-dependent and/or temperature-independent voltages can be setfor selected and/or unselected word lines which communicate with thecontrol gates of selected and/or unselected storage elements.

For instance, a temperature-dependent read or verify voltage can beapplied to a selected word line of one or more non-volatile storageelements undergoing read or verify operations. It is also possible forthe temperature-dependent read or verify voltage to vary withtemperature according to a first temperature coefficient, and for thetemperature-dependent bias voltage to vary with temperature according toa second temperature coefficient which differs from the firsttemperature coefficient.

Thus, the temperature-dependence of the biasing and of the reading orverifying can be optimally tailored. For example, while the body biasvalue could change from 0 V at −15° C. to −0.4 V at 100° C., indicatingthat the temperature coefficient is +0.4/100° C., the read voltage couldincrease from 3 V at −15° C. to 3.4 V at 100° C., indicating that thetemperature coefficient is +0.4 V for a 100° C. increase in temperature.Thus, the polarity and/or magnitude of the temperature coefficients candiffer. A similar approach can be taken for the voltages applied to theunselected word lines, e.g., such that the temperature-dependentvoltages applied to the unselected word lines vary with temperatureaccording to a third temperature coefficient, and thetemperature-dependent bias voltage varies with temperature according tothe second temperature coefficient which differs from the thirdtemperature coefficient. Further, the temperature coefficient for thevoltages applied to the unselected word lines can differ from thetemperature coefficient for the voltage applied to the selected wordline. Steps 858 and 860 correspond to steps 840 and 845, respectively,discussed previously.

FIG. 8c depicts a process in which a body bias is applied via atemperature-independent voltage to the p-well and n-well (step 870), orto the p-well while grounding the n-well (step 872), while atemperature-dependent voltage is applied to the source and/or drain sideof the set of storage elements (step 874). Thus, in one possibleapproach, the p-well and n-well voltage are held constant while thesource line (source side), bit line (drain side) and selected storageelement control gate voltages vary with temperature according to onetemperature coefficient, and Vread for the unselected storage elementsvary with temperature according to another temperature coefficient,during a read or verify operation. In one scenario, at highertemperatures, above room temperature, the source line, bit line andselected storage element control gate voltages increase while Vreaddecreases.

Steps 800-815 are the same as discussed previously. Further, at step876, temperature-dependent and/or temperature-independent voltages canbe set for selected and/or unselected word lines which communicate withthe control gates of selected and/or unselected storage elements, asdiscussed previously.

For instance, a temperature-dependent read or verify voltage can beapplied to a selected word line of one or more non-volatile storageelements undergoing read or verify operations. It is also possible forthe temperature-dependent read or verify voltage to vary withtemperature according to a first temperature coefficient, and for thetemperature-dependent voltage applied to the source and/or drain side ofthe set of storage elements to vary with temperature according to asecond temperature coefficient which differs from the first temperaturecoefficient.

A similar approach can be taken for the voltages applied to theunselected word lines, e.g., such that the temperature-dependentvoltages applied to the unselected word lines vary with temperatureaccording to a third temperature coefficient, and thetemperature-dependent voltage applied to the source and/or drain side ofthe set of storage elements varies with temperature according to thesecond temperature coefficient which differs from the third temperaturecoefficient. Further, the temperature coefficient for the voltagesapplied to the unselected word lines can differ from the temperaturecoefficient for the voltage applied to the selected word line. Steps 878and 880 correspond to steps 840 and 845, respectively, discussedpreviously.

FIG. 9a depicts voltages applied to a set 900 of word lines during aprogram operation. The word lines include WL0 through WL7. In thisexample, WL4 is the selected word line so storage elements associatedwith WL4 receive a program voltage V_(PGM). WL0-WL3 and WL5-WL7 areunselected word lines. A pass voltage, V_(PASS), is applied to theunselected word lines in one example of a self-boosting scheme.

In read and verify operations, read and/or verify voltages which areapplied to the word lines can be temperature independent. For example,FIG. 9b depicts voltages applied to a set of word lines during a read orverify operation. During a read or verify operation, in which one ormore storage elements associated with WL4 are read or verified, forinstance, the unselected word lines WL0-WL3 and WL5-WL7 are raised to aread pass voltage, V_(READ), and the selected word line WL4 is connectedto a control gate voltage, V_(CG), a level of which is specified foreach read and verify operation, in order to determine whether a V_(TH)of the concerned storage element or elements is above or below suchlevel.

V_(CG) is a temperature-independent voltage which is applied to aselected word line in a set of word lines during biasing of thesubstrate to determine a condition, such as a verify or read level, ofat least one non-volatile storage element which is associated with theselected word line. The biasing is set to vary with temperature tocompensate one or more temperature-varying characteristics ofnon-volatile storage elements of the set of non-volatile storageelements. These characteristics can include a threshold voltage, slopeof sub-threshold voltage, depletion layer width and noise. The V_(READ)voltages are temperature-independent voltages which are applied tounselected word lines during the biasing. V_(SGD) and V_(SGS) cansimilarly be temperature-independent, in one possible implementation

FIG. 10a depicts a change in threshold voltage as a function of wordline position. Body bias can also be used to compensate for word-linedependent performance variations in a non-volatile storage system. Forexample, during read/verify operations, higher word lines in a NANDstring, e.g., word lines at the drain side of a NAND string, have alower body-to-source voltage (V_(BS)) than word lines at the source sideof a NAND string. This can occur because the body is grounded, and thesource potential of higher word lines is higher due to the potentialdrop across the lower transistors of the NAND string. As a result, for agiven programming state, V_(TH) levels of storage elements associatedwith the higher word lines is increased relative to storage elementsassociated with the lower word lines, as depicted in FIG. 10a. Further,V_(TH) distributions of the storage elements associated with the higherword lines can differ from those of the storage elements associated withthe lower word lines. However, conventionally, voltages applied to theword lines for programming, read or verify operations are not changedbased on word line position. The changes of V_(TH) across the NANDstring prevent a designer from choosing optimal program, read and verifyvoltages, and can result in higher read/write disturbs, reduction ofV_(TH) window, increased programming times, higher error rates and/ornon-optimal NAND string resistance. Moreover, these issues will be evenmore of a concern for future NAND strings which have more storageelements, e.g., 64-element NAND strings.

FIGS. 10b-10d depict example control curves of body bias as a functionof word line position. To address these issues, a body bias can beapplied to reduce or eliminate variations in V_(TH) due to word lineposition. For example, as depicted by the control curve of in FIG. 10b,which can represent a linear or non-linear function, when a word line isselected for a program, read or verify operation, a lower body potentialcan be applied when the selected word line is a lower, source-side, wordline, and a higher body potential can be applied when the selected wordline is a higher, drain-side, word line. This technique can tighten thewidth of the natural distribution of V_(TH) values for the NAND arrayand thus enable a choice of optimal program, read and verify voltages.In one approach (curve 1000), V_(BS) increase gradually with theselected word line position. In another approach (curve 1001), V_(BS)increases in a step-wise manner to reduce the number of adjustments. Forexample, two V_(BS) levels can be set; one for WL0-WL15 and one forWL16-WL31 (assuming a 32-element NAND string). In this case, a firstbias is applied when the selected word line is in a first group ofmultiple word lines, and a second bias is applied when the selected wordline is in a second group of multiple word lines. Additional groups maybe used as well.

In another aspect, a different body bias is applied when a selected wordline is an end word line, e.g., one or more word lines which areadjacent to the source or drain side of a NAND string. This approach isbased on the observation that gate-induced drain leakage (GIDL) is afunction of body potential. Applying a different substrate bias when theselected word line is WL0 or WL31, in a 32-element NAND string, asdepicted in FIG. 10c, for instance, can reduce GIDL. In another possibleapproach, depicted in FIG. 10d, V_(BS) is increased gradually forselected word lines which are closer to the drain-side of a NAND string,while a further variation is exhibited when the selected word line is anend word line.

Generally, the optimal control curve for a particular non-volatilestorage device can be determined based on test results and/ortheoretical results which identify the selected word line-dependentbehavior of the compensated parameters.

The different body potentials can be applied for program, verify andread operations (or just verify and read operations) of different wordlines in a NAND string. Essentially, the body potential becomes afunction of the word line number. Lower body potentials are applied tolower word lines such as WL0, WL1, WL2, etc., while higher bodypotentials are applied to higher word lines such as WL29, WL30, WL31,etc., so that V_(BS) is equalized for all word lines. As a result,natural V_(TH) distributions of a NAND array can be tighter, resultingin many benefits such as reduction of disturbs, larger V_(TH) window,reduced programming times, higher reliability and/or improved NANDstring resistance. Further, the benefits obtained from this techniquewill be even greater when 64-element NAND strings are used.

FIG. 10e depicts a process for operating non-volatile storage in whichbody bias is varied based on selected word line position. Step 1002includes beginning a program, read or verify operation. Step 1005includes identifying the selected word line, e.g., the word lineassociated with one or more storage elements which are undergoing theprogram, read or verify operation. Step 1010 includes setting the bodybias level based on the position of the selected word line, as discussedabove. Step 1015 includes applying the bias. For example, this caninvolve applying a voltage to the p-well and n-well of the substrate(step 1020), applying a voltage to the p-well while grounding the n-well(step 1025) or grounding the body and applying a voltage to the sourceand/or drain side of the set of storage elements (step 1030). At step1035, the program, read or verify operation is performed. This caninvolve applying a first voltage, such as a control gate read or verifyvoltage, to a selected word line of a set of word lines to determine acondition of at least one non-volatile storage element of a set ofnon-volatile storage elements, where the at least one non-volatilestorage element is in communication with the selected word line, and theset of non-volatile storage elements is in communication with the set ofword lines. The substrate is biased while applying the first voltage,and a level of the biasing varies based on a position of the selectedword line in the set of word lines. For example, the biasing level canincrease when the selected word line is closer to a drain-side of theset of word lines, and/or the biasing level can vary based on whether ornot the selected word line is an end word line in the set of word lines.

At decision step 1040, if there is a next operation to perform, thecontrol flow returns to step 1005, where the selected word line involvedin the next operation is identified. If the next operation involves thesame selected word line, no change to the body bias is needed. If thereis a new selected word line, a new body bias level may be set at step1010. At decision step 1040, if there is no next operation to perform,the program, read or verify operation ends (step 1045).

FIG. 11 depicts a process for operating non-volatile storage in whichbody bias is varied based on an error metric. Body bias can also be setadaptively to reduce read errors in a non-volatile storage system. Whilereverse body bias improves the subthreshold slope, it can cause junctionleakage currents to increase. Also, maintaining a constant value ofreverse bias can be problematic, e.g., when a source voltage other than0 V is used. So, the optimal body bias value is not always the mostreverse biased one. Changing the body bias value based on an error countis an alternative technique for selecting an optimal body bias value.

A memory array can be divided into a large number of blocks of storageelements, where the block is erased as a unit. Further, each block canbe divided into a number of pages, e.g., 8, 32, 64 or more pages, wherethe page is programmed as a unit. A page can store one or more sectors,where a sector includes user data and overhead data, such as an errorcorrecting or error detecting code bits that have been calculated fromthe user data of the sector. A sector of user data is typically 512bytes, while overhead data is typically an additional 16-20 bytes. Theerror correcting or error detecting code bits can be calculated whendata is being programmed into the array. Subsequently, when reading thesectors, an error count can be determined based on errors detected bythe error correcting or detecting code. Error correcting codes (ECCs),such as Hamming codes, can detect and correct some errors, while errordetecting codes, such as those using parity bits or checksums, can onlydetect errors without correcting them. In particular, the read sectordata is run through the error correcting or detecting code to see if theoutput is consistent with the error correcting or detecting bits. If theoutput is not consistent, there is an error in the sector. Accordingly,an error metric such as an error count can be generated based on anumber of errors which are detected for a sector or other unit. Thecount may include all detected errors, including those which can becorrected, or only errors which cannot be corrected, for instance. Thecount can be expressed as a raw count, a percentage, or other errormetric.

For example, consider a NAND array in which ECC bits are used to correctread errors, each set of ECC bits handles 512 bytes of user data and theECC can correct a maximum of eight errors. The number of bit errors inthe ECC is monitored during each read of the array. When the number ofbit errors exceeds a threshold, such as four errors, the body biasapplied to these 512 bytes is reduced the next time data is written orverified. Further, when the data is read again, the number of bit errorsis monitored and it is seen if the number of failed bits is reduced.This procedure may be repeated, e.g., three times, to obtain an averagenumber of failed bits. If the average number of failed bits is reducedwith the new body bias value, the new body bias value is retained.Otherwise, in one approach, V_(BS) is made higher than the initial valueand subsequent error counts are monitored to determine if the new V_(BS)is appropriate. In another approach, the body bias is increased above aninitial value if the error metric exceeds a threshold, then decreasedbelow the initial value if the increased value does not result in fewererrors. V_(BS) could also be changed in proportion to the error count,so that a larger error count results in a larger change in V_(BS). Theproportion can be linear or non-linear. Further, while the exampledescribed considered only 512 bytes of data, one could apply this kindof adaptive body bias process across an entire block or plane.

The above-described process is summarized in FIG. 11, in which step 1100includes beginning a read operation and step 1105 includes setting aninitial body bias level. Step 1110 includes applying the bias. Forexample, this can involve applying a voltage to the p-well and n-well ofthe substrate (step 1115), applying a voltage to the p-well whilegrounding the n-well (step 1120) or grounding the body and applying avoltage to the source and/or drain side of the set of storage elements(step 1125). At step 1130, the read operation is performed and, at step1135, an error metric such as an error count is determined. In oneapproach, the error metric is based on multiple read operations.Further, the error metric can be for one or more pages, blocks or othersets of storage elements. In one approach, the error metric isdetermined from multiple error metrics obtained from readingnon-volatile storage elements in multiple sets of non-volatile storageelements. An average or mean of the multiple error metrics can be used,for instance. At decision step 1140, if the error metric exceeds athreshold, a new body bias level is set for a next read operation and,at step 1155, the read operation ends. At decision step 1140, if theerror metric does not exceed the threshold, the current body bias levelis used for the next read operation (step 1145).

Thus, the process involves reading non-volatile storage elements in atleast one set of non-volatile storage elements while biasing a substrateat a first bias level, and based on the reading, determining an errormetric. If the error metric exceeds a threshold, a second bias level isdetermined for biasing the substrate when performing a subsequent readof non-volatile storage elements in the at least one set of non-volatilestorage elements.

FIG. 12a depicts a change in body bias as a function of a number ofprogramming cycles. Body bias can also be set adaptively based onprogramming cycles experienced by a memory device as the memory deviceages. The performance of cycled memory devices can vary from that offresh devices. For example, cycled memory devices typically programfaster than fresh devices due to charge trapping. In particular, as anon-volatile memory device undergoes many programming cycles, chargebecomes trapped in the insulator or dielectric between the floating gateand the channel region. This trapping of charge shifts the thresholdvoltage to a higher level, which allows the memory element to programfaster while also making it harder to erase the charge in the element.Cycled devices also have higher sub-threshold slope, which makes sensingdifficult.

Various advantages can be achieved by setting the body bias level as afunction of cycling. In one approach, the subthreshold slope degradationwith cycling can be compensated with applying a lower body bias valuewith cycling, as depicted in FIG. 12a, which represents a linear ornon-linear control curve. Further, this varying of body bias withcycling can be performed over an entire plane of devices or even acrossan entire chip, since wear leveling can ensure that cycling isreasonably uniform over the entire chip.

Generally, the optimal control curve for a particular non-volatilestorage device can be determined based on test results and/ortheoretical results which identify the cycle-dependent behavior of thecompensated parameters. For instance, while the example control curve ofFIG. 12a depicts a decrease in body bias with programming cycles, theoptimal body bias can increase or decrease with cycling depending ondifferent factors.

The above-described process is summarized in FIG. 12b, which depicts aprocess for operating non-volatile storage in which body bias is variedbased on a number of programming cycles. Step 1200 includes beginning aprogram, read or verify operation and step 1205 includes retrieving acount of programming cycles. In one approach, the cycle count is storedas data in the non-volatile storage system. This data can be read toobtain a cycle count which is used to determine the body bias level.Step 1210 includes setting a body bias level based on the count ofprogramming cycles, and step 1215 includes applying the bias. Forexample, this can involve applying a voltage to the p-well and n-well ofthe substrate (step 1220), applying a voltage to the p-well whilegrounding the n-well (step 1225) or grounding the body and applying avoltage to the source and/or, drain side of the set of storage elements(step 1230). At step 1235, the program, read or verify operation isperformed and, at step 1240, the count of programming cycles is updated.At step 1245, the program, read or verify operation ends.

The process thus involves tracking programming cycles experienced by atleast one set of non-volatile storage elements, and biasing thesubstrate at a bias level during operations performed on the at leastone set of non-volatile storage elements, where the bias level is basedon the tracking. In one approach, the bias level decreases as the numberof programming cycles increases. The tracking of the programming cyclescan include separately tracking programming cycles experienced bydifferent sets of non-volatile storage elements which are formed ondifferent portions of a substrate, in which case an aggregate usagemetric can be determined based on the separate tracking, and the biaslevel is based on the aggregate usage metric. For example, the usagemetric for each set can be a count of programming cycles for the set,and the aggregate usage metric can be an average or mean of theindividual usage metrics. In another approach, the tracking of theprogramming cycles can include separately tracking programming cyclesexperienced by different sets of non-volatile storage elements which areformed on different portions of a substrate, in which case the differentportions of the substrate are biased at different bias levels duringoperations performed on the different sets of non-volatile storageelements, and the different bias levels are based on the tracking

FIG. 13a depicts non-volatile storage in which planes and blocks of achip have a common body bias. Each chip, plane, block and/or pageassociated with a non-volatile storage system can receive its own,separate optimal body bias which maximizes its performance. In somecases, a device such as a secure digital (SD) memory card could haveseveral stacked chips. The storage elements can be considered to bearranged in a hierarchy, where the chip level represents the highestlevel and the plane, block and/or page levels represent successivelylower levels. A chip may include a memory device, a plane may includemultiple blocks, a block may include a set of non-volatile storageelements in communication with a set of word lines, and a page mayinclude selected non-volatile storage elements (e.g., odd or even)associated with a given word line, in one possible approach. The optimalbody bias for each chip, plane, block and/or page can vary based onfactors such as subthreshold slope, cell source noise, cycling, errorcount and the like. For example, one chip, plane, block and/or page mayhave experienced more cycles than another. In another example, one chip,plane, block and/or page may have a different bias than another forreducing an error count, as discussed previously. In one exampleimplementation, a chip 1300 includes a p-well 1305 in which a plane1310, with blocks 1312, 1314 and 1316 are formed, and a plane 1320, inwhich blocks 1322, 1324 and 1326 are formed. In this case, a common bodybias is applied to each of the components via the p-well 1305, in oneapproach.

The body bias value for any block or page can be stored in a table orother data structure in a control, where the body bias value can beobtained by giving the block or page address. Before reading each blockor page, the data stored in the above mentioned table is accessed toobtain the body bias value to be used.

FIG. 13b depicts non-volatile storage in which planes of a chip haveseparate body biases. A chip 1330 includes a p-well 1348 in which aplane 1340, with blocks 1342, 1344 and 1346 are formed, and a plane1350, in which blocks 1352, 1354 and 1356 are formed. In this case,separate body biases are applied to each of the planes 1340 and 1350 viathe p-wells 1348 and 1358, respectively.

Similarly, different blocks of a chip can have their own optimal bodybias values. It must be noted that although different blocks could sharethe same p-well, they can be accessed at different periods of time, thusallowing different body bias values to be used when they are accessed.

FIG. 14a depicts non-volatile storage in which a body bias is appliedfor storage elements associated with an even page. An ith block ofstorage elements is formed in a p-well 1400. The storage elements arearranged in NAND strings which extend vertically in the figure, whileword lines WL0_i through WL3_i, which are in communication with thestorage elements, and select gate lines SGS_i and SGD_i, extendhorizontally. Here, alternate storage elements along a word line, e.g.,WL3_i, store data for an even page. Thus, a particular body bias can beapplied to the p-well 1400 when program, read or verify operations areperformed involving data for this particular even page. Further, adifferent body bias can be applied to the p-well 1400 when program, reador verify operations are performed involving data for another particulareven page, such as an even page involving WL2_i. Similarly, a differentbody bias can be applied when program, read or verify operations areperformed involving data for an odd page involving WL3_i or other wordline, as depicted by FIG. 14b. Specifically, FIG. 14b depictsnon-volatile storage in which a body bias is applied for storageelements associated with an odd page. Alternate storage elements along aword line, e.g., WL3_i, store data for an odd page. Thus, a particularbody bias can be applied to the p-well 1400 when program, read or verifyoperations are performed involving data for this particular odd page.

The above-described process is summarized in FIG. 15, which depicts aprocess for operating non-volatile storage in which separate body biasesare applied at the chip, plane, block and/or page level. Step 1500includes beginning a program, read or verify operation. Step 1502includes reading a memory to obtain desired body bias levels for one ormore chips, planes, blocks and/or pages. For example, the different bodybias values can be retrieved from a table or other data structure. Inone possible approach, the different body bias values are stored innon-volatile storage elements associated with the one or more chips,planes, blocks and/or pages. Step 1505 includes setting body bias levelsfor one or more chips, planes, blocks and/or pages involved in theoperations, based on the desired body bias levels. Step 1510 includesapplying the biases. For example, this can involve applying voltages tothe p-well and n-well of the substrate (step 1515), applying voltages tothe p-well while grounding the n-well (step 1520) and/or grounding thebody and applying voltages to the source and/or drain sides of thedifferent sets of storage elements, e.g., at the chip, plane, blockand/or page level (step 1525). At step 1530, the program, read or verifyoperation is performed and, at step 1535, the program, read or verifyoperation ends.

The process thus includes performing operations on non-volatile storageelements in different sets of non-volatile storage elements, where thedifferent sets of non-volatile storage elements are formed on differentportions of a substrate, and biasing the different portions of thesubstrate separately while the operations are performed. For example,the different sets of non-volatile storage elements can be in differentplanes of a chip, where each plane includes multiple blocks, and eachblock is erasable as a unit. In another approach, the different sets ofnon-volatile storage elements are in different blocks, where each blockis erasable as a unit. In another approach, the different sets ofnon-volatile storage elements are in different pages, and each page isprogrammed as a unit. At least two different portions of the substratecan be biased at different bias levels. Further, the different portionsof the substrate can be biased separately and concurrently.

FIG. 16 depicts an example of an array or plane of storage elements,including different sets of NAND strings. Generally, the energy consumedby applying a body bias can be reduced by having multiple p-wells in aplane or splitting the source wiring mesh into multiple “mini-meshes.”Multiple p-wells in a plane reduce the time consumption/capacitive loadinvolved with charging/discharging the body and also the forward biasdiode current of the body/source junctions, but this happens at theexpense of chip area. Another approach which can reduce energyconsumption involves maintaining a common p-well while splitting thesource mesh into multiple “mini-meshes” and floating the sources of theunused “mini-meshes” to reduce the forward bias diode current of thesource/body junction of selected storage elements of the array. This canbe advantageous even if source resistance increases. A mini-mesh caninclude a set of NAND strings.

For example, the memory array 1600 includes NAND string set “A” 1650,having NAND strings 1652, 1654, . . . , 1656, NAND string set “B” 1660,having NAND strings 1662,1664, . . . , 1666, and NAND string set “C”1670, having NAND strings 1672, 1674, . . . , 1676, all formed in p-well1605. Along each column, bit lines are coupled to the drain terminalsrespectively, of the drain select gates for the NAND strings. Forexample, for the NAND string set “A” 1650, bit lines 1606, 1607, . . . ,1608 are coupled to the drain terminals 1626, 1627, . . . , 1628,respectively, of the drain select gates for the NAND strings 1652, 1654,. . . , 1656. Further, along each row of NAND strings, a source voltage(V_(SOURCE)) supply line may connect all the source terminals of thesource select gates of the NAND strings. For example, V_(SOURCE) supplyline “A” 1658 connects the source terminals 1636, 1637, . . . , 1638 ofthe source select gates of the NAND strings 1652, 1654, . . . , 1656.Similarly, V_(SOURCE) supply line “B” 1668 connects the source terminalsof the source select gates of the NAND strings 1662, 1664, . . . , 1666,and V_(SOURCE) supply line “C” 1678 connects the source terminals of thesource select gates of the NAND strings 1672, 1674, . . . , 1676.Further details regarding an example of a NAND architecture array andits operation as part of a memory system is found in U.S. Pat. Nos.5,570,315; 5,774,397; and 6,046,935.

The above-described process is summarized in FIG. 17, which depicts aprocess for operating non-volatile storage in which different bodybiases are applied to different sets of NAND strings. Step 1700 includesbeginning program, read or verify operations for a first set of NANDstrings (e.g., NAND string set “A” 1650 in FIG. 16) while at least asecond set of NAND strings (e.g., NAND string set “B” 1660 and “C” 1670in FIG. 16) is inactive or unused, e.g., program, read or verifyoperations are not being conducted on the second set of NAND strings.The first and second sets of NAND strings are on a common p-well of asubstrate. Step 1705 includes setting a bias level for the first set ofNAND strings, and step 1710 includes applying the bias. This can beachieved by applying a first voltage (V_(SOURCE)) to the source side ofthe first set of NAND strings via a first source voltage supply line,e.g., line 1658 (step 1715). Step 1720 includes applying a secondvoltage (V_(B)) to the p-well and n-well, or to the p-well whilegrounding the n-well, where a difference between first and secondvoltages is based on a desired bias level (V_(BS)). Step 1725 includesfloating, or providing a fixed voltage to, the second set of NANDstrings via a second source voltage supply line (e.g., line 1668). As aresult, little p-n junction current flows between the source and thebody for the non-volatile storage elements in the second set of NANDstrings, so energy consumption is reduced. As a further example, if NANDstring set “C” 1670 is inactive, the third set of NAND strings can floator receive a fixed voltage via the source voltage supply line “C” 1678.

Moreover, the fixed voltage can be set based on the bias level for thefirst set of NAND strings. For example, one implementation is: V_(B)=0.4V, V_(SOURCE)=0 V (for set A) and V_(SOURCE) (for set B)=0.4 V. In thiscase, V_(SOURCE) (for set B)=V_(B), the second voltage which is appliedto the p-well and n-well, or to the p-well while grounding the n-well.Essentially, the V_(SOURCE) for the unused set of NAND stringscounteracts the applied body bias. Note also that steps 1715, 1720 and1725 can be performed at the same time, in one approach. At step 1730,the operations are performed on the first set of NAND strings, e.g., toone or more non-volatile storage elements in the first set of NANDstrings.

Once operations involving the first set of NAND strings are completed,program, read or verify operations for the second set of NAND stringscan begin while the first set of NAND strings is inactive (step 1735).Step 1740 includes setting a bias level for the second set of NANDstrings, and step 1745 includes applying the bias. Note that the bodybias can be the same or different for the different sets of NANDstrings. Step 1750 includes applying a third voltage (V_(SOURCE)) to thesource side of the second set of NAND strings via a second sourcevoltage supply line, e.g., line 1668 (FIG. 16). Step 1755 includesapplying a fourth voltage (V_(B)) to the p-well and n-well, or to thep-well while grounding the n-well, where a difference between third andfourth voltages is based on a desired bias level (V_(BS)). Step 1760includes floating, or providing a fixed voltage to, the first set ofNAND strings via the first source voltage supply line (e.g., line 1658).Note that steps 1750, 1755 and 1760 can be performed at the same time,in one approach. At step 1765, the operations are performed on thesecond set of NAND strings, e.g., to one or more non-volatile storageelements in the second set of NAND strings.

FIG. 18 depicts a process for setting a body bias level based onmultiple factors. As discussed, body bias can be used to address anumber of different issues. The body bias can be set to address anindividual issue, or to address multiple issues concurrently. Forexample, step 1800 includes beginning a body bias selection process.Step 1805 includes considering a temperature-dependent reference signal.Step 1810 includes considering a selected word line position. Step 1815includes considering a number of programming cycles. Step 1820 includesconsidering an error metric. Step 1825 includes considering a chip,plane, block or page status involved in a program, read or verifyoperation. Step 1830 includes considering a NAND string set involved ina program, read or verify operation. Finally, step 1835 involves settinga body bias level. In some cases, different body bias levels wouldresult from consideration of different factors alone, in which case anoptimization can be performed to arrive at a final body bias leveldetermination. For example, an average of the different body bias levelscan be taken to arrive at the final body bias level. Or, the differentbody bias levels can be weighted based on the relative importance of thefactor on which they are based. For instance, a body bias level based ontemperature may be weighted as being more important than a body biaslevel based on selected word line position.

FIG. 19 is a block diagram of a non-volatile memory system using singlerow/column decoders and read/write circuits. The diagram depicts amemory device 1996 having read/write circuits for reading andprogramming a page of storage elements in parallel, according to oneembodiment of the present invention. Memory device 1996 may include oneor more memory die. One example of a memory die or chip 1998 includes atwo-dimensional array of storage elements 1600, control circuitry 1910,and read/write circuits 1965. In some embodiments, the array of storageelements can be three dimensional. The memory array 1600 is addressableby word lines via a row decoder 1930 and by bit lines via a columndecoder 1960. The read/write circuits 1965 include multiple sense blocks1900 and allow a page of storage elements to be read or programmed inparallel. Typically a controller 1950 is included in the same memorydevice 1996 (e.g., a removable storage card) as the one or more memorydie 1998. Commands and Data are transferred between the host andcontroller 1950 via lines 1920 and between the controller and the one ormore memory die 1998 via lines 1918.

The control circuitry 1910 cooperates with the read/write circuits 1965to perform memory operations on the memory array 1600. The controlcircuitry 1910 includes a state machine 1912, an on-chip address decoder1914, a body bias control circuit 1915, and a power control module 1916.The body bias control circuit 1915 determines one or more body biaslevels which are to be applied to the memory array 1600. The body biaslevel determination may be made based on various factors, as discussedpreviously. The state machine 1912 provides chip-level control of memoryoperations. The on-chip address decoder 1914 provides an addressinterface between that used by the host or a memory controller to thehardware address used by the decoders 1930 and 1960. The power controlmodule 1916 controls the power and voltages supplied to the word linesand bit lines during memory operations.

In some implementations, some of the components of FIG. 19 can becombined. In various designs, one or more of the components (alone or incombination), other than storage element array 1600, can be thought ofas a managing circuit. For example, one or more managing circuits mayinclude any one of or a combination of control circuitry 1910, statemachine 1912, decoders 1914/1960, power control 1916, sense blocks 1900,read/write circuits 1965, controller 1950, etc.

FIG. 20 is a block diagram of a non-volatile memory system using dualrow/column decoders and read/write circuits. Here, another arrangementof the memory device 1996 shown in FIG. 19 is provided. Access to thememory array 1600 by the various peripheral circuits is implemented in asymmetric fashion, on opposite sides of the array, so that the densitiesof access lines and circuitry on each side are reduced by half Thus, therow decoder is split into row decoders 1930A and 1930B and the columndecoder into column decoders 1960A and 1960B. Similarly, the read/writecircuits are split into read/write circuits 1965A connecting to bitlines from the bottom and read/write circuits 1965B connecting to bitlines from the top of the array 1600. In this way, the density of theread/write modules is essentially reduced by one half. The device canalso include a controller, as described above for the device of FIG. 19.

FIG. 21 is a block diagram depicting one embodiment of the sense block1900 of FIG. 19. A sense block is used to determine the programmingcondition of a non-volatile storage element. An individual sense block1900 is partitioned into a core portion, referred to as a sense module1980, and a common portion 1990. In one embodiment, there will be aseparate sense module 1980 for each bit line and one common portion 1990for a set of multiple sense modules 1980. In one example, a sense blockwill include one common portion 1990 and eight sense modules 1980. Eachof the sense modules in a group will communicate with the associatedcommon portion via a data bus 1972. For further details refer to U.S.Patent Application Pub No. 2006/0140007, titled “Non-Volatile Memory &Method with Shared Processing for an Aggregate of Sense Amplifiers”published Jun. 29, 2006, and incorporated herein by reference in itsentirety.

Sense module 1980 comprises sense circuitry 1970 that determines whethera conduction current in a connected bit line is above or below apredetermined threshold level. Sense module 1980 also includes a bitline latch 1982 that is used to set a voltage condition on the connectedbit line. For example, a predetermined state latched in bit line latch1982 will result in the connected bit line being pulled to a statedesignating program inhibit (e.g., Vdd).

Common portion 1990 comprises a processor 1992, a set of data latches1994 and an I/O Interface 1996 coupled between the set of data latches1994 and data bus 1920. Processor 1992 performs computations. Forexample, one of its functions is to determine the data stored in thesensed storage element and store the determined data in the set of datalatches. The set of data latches 1994 is used to store data bitsdetermined by processor 1992 during a read operation. It is also used tostore data bits imported from the data bus 1920 during a programoperation. The imported data bits represent write data meant to beprogrammed into the memory. I/O interface 1996 provides an interfacebetween data latches 1994 and the data bus 1920.

During read or sensing, the operation of the system is under the controlof state machine 1912 that controls the supply of different control gatevoltages to the addressed storage element. As it steps through thevarious predefined control gate voltages corresponding to the variousmemory states supported by the memory, the sense module 1980 may trip atone of these voltages and an output will be provided from sense module1980 to processor 1992 via bus 1972.

At that point, processor 1992 determines the resultant memory state byconsideration of the tripping event(s) of the sense module and theinformation about the applied control gate voltage from the statemachine via input lines 1993. It then computes a binary encoding for thememory state and stores the resultant data bits into data latches 1994.In another embodiment of the core portion, bit line latch 1982 servesdouble duty, both as a latch for latching the output of the sense module1980 and also as a bit line latch as described above.

It is anticipated that some implementations will include multipleprocessors 1992. In one embodiment, each processor 1992 will include anoutput line (not depicted in FIG. 21) such that each of the output linesis wired-OR'd together. In some embodiments, the output lines areinverted prior to being connected to the wired-OR line. Thisconfiguration enables a quick determination during the programverification process of when the programming process has completedbecause the state machine receiving the wired-OR can determine when allbits being programmed have reached the desired level. For example, wheneach bit has reached its desired level, a logic zero for that bit willbe sent to the wired-OR line (or a data one is inverted). When all bitsoutput a data 0 (or a data one inverted), then the state machine knowsto terminate the programming process. Because each processorcommunicates with eight sense modules, the state machine needs to readthe wired-OR line eight times, or logic is added to processor 1992 toaccumulate the results of the associated bit lines such that the statemachine need only read the wired-OR line one time. Similarly, bychoosing the logic levels correctly, the global state machine can detectwhen the first bit changes its state and change the algorithmsaccordingly.

During program or verify, the data to be programmed is stored in the setof data latches 1994 from the data bus 1920. The program operation,under the control of the state machine, comprises a series ofprogramming voltage pulses applied to the control gates of the addressedstorage elements. Each programming pulse is followed by a read back(verify) to determine if the storage element has been programmed to thedesired memory state. Processor 1992 monitors the read back memory staterelative to the desired memory state. When the two are in agreement, theprocessor 1992 sets the bit line latch 1982 so as to cause the bit lineto be pulled to a state designating program inhibit. This inhibits thestorage element coupled to the bit line from further programming even ifprogramming pulses appear on its control gate. In other embodiments theprocessor initially loads the bit line latch 1982 and the sensecircuitry sets it to an inhibit value during the verify process.

Data latch stack 1994 contains a stack of data latches corresponding tothe sense module. In one embodiment, there are three data latches persense module 1980. In some implementations (but not required), the datalatches are implemented as a shift register so that the parallel datastored therein is converted to serial data for data bus 1920, and viceversa. In the preferred embodiment, all the data latches correspondingto the read/write block of m storage elements can be linked together toform a block shift register so that a block of data can be input oroutput by serial transfer. In particular, the bank of r read/writemodules is adapted so that each of its set of data latches will shiftdata in to or out of the data bus in sequence as if they are part of ashift register for the entire read/write block.

Additional information about the structure and/or operations of variousembodiments of non-volatile storage devices can be found in (1) U.S.Patent Application Pub. No. 2004/0057287, “Non-Volatile Memory AndMethod With Reduced Source Line Bias Errors,” published on Mar. 25, 2004(issued as U.S. Pat. No. 7,196,931 on Mar. 27, 2007); (2) U.S. PatentApplication Pub No. 2004/0109357, “Non-Volatile Memory And Method withImproved Sensing,” published on Jun. 10, 2004 (issued as U.S. Pat. No.7,023,736 on Apr. 4, 2006); (3) U.S. patent application Ser. No.11/015,199 titled “Improved Memory Sensing Circuit And Method For LowVoltage Operation,” filed on Dec. 16, 2004 (issued as U.S. Pat. No.7,046,568 on May 16, 2006); (4) U.S. patent application Ser. No.11/099,133, titled “Compensating for Coupling During Read Operations ofNon-Volatile Memory,” filed on Apr. 5, 2005 (issued as U.S. Pat. No.7,196,928 on Mar. 27, 2007); and (5) U.S. patent application Ser. No.11/321,953, titled “Reference Sense Amplifier For Non-Volatile Memory,filed on Dec. 28, 2005 (issued as U.S. Pat. No. 7,327,619 on Feb. 5,2008). All five of the immediately above-listed patent documents areincorporated herein by reference in their entirety.

FIG. 22 depicts an example of an organization of a memory array intoblocks for odd-even and all bit line memory architectures. Exemplarystructures of the memory array 1600 of FIG. 16 are described. As oneexample, a NAND flash EEPROM is described that is partitioned into 1,024blocks. The data stored in each block can be simultaneously erased. Inone embodiment, the block is the minimum unit of storage elements thatare simultaneously erased. In each block, in this example, there are8,512 columns corresponding to bit lines BL0, BL1, BL8511. In oneembodiment referred to as an all bit line (ABL) architecture(architecture 2210), all the bit lines of a block can be simultaneouslyselected during read and program operations. Storage elements along acommon word line and connected to any bit line can be programmed at thesame time.

In the example provided, four storage elements are connected in seriesto form a NAND string. Although four storage elements are shown to beincluded in each NAND string, more or less than four can be used (e.g.,16, 32, 64 or another number). One terminal of the NAND string isconnected to a corresponding bit line via a drain select gate (connectedto select gate drain lines SGD), and another terminal is connected toc-source via a source select gate (connected to select gate source lineSGS).

In another embodiment, referred to as an odd-even architecture(architecture 2200), the bit lines are divided into even bit lines (BLe)and odd bit lines (BLo). In the odd/even bit line architecture, storageelements along a common word line and connected to the odd bit lines areprogrammed at one time, while storage elements along a common word lineand connected to even bit lines are programmed at another time. Data canbe programmed into different blocks and read from different blocksconcurrently. In each block, in this example, there are 8,512 columnsthat are divided into even columns and odd columns. In this example,four storage elements are shown connected in series to form a NANDstring. Although four storage elements are shown to be included in eachNAND string, more or fewer than four storage elements can be used.

During one configuration of read and programming operations, 4,256storage elements are simultaneously selected. The storage elementsselected have the same word line and the same kind of bit line (e.g.,even or odd). Therefore, 532 bytes of data, which form a logical page,can be read or programmed simultaneously, and one block of the memorycan store at least eight logical pages (four word lines, each with oddand even pages). For multi-state storage elements, when each storageelement stores two bits of data, where each of these two bits are storedin a different page, one block stores sixteen logical pages. Other sizedblocks and pages can also be used.

For either the ABL or the odd-even architecture, storage elements can beerased by raising the p-well to an erase voltage (e.g., 20 V) andgrounding the word lines of a selected block. The source and bit linesare floating. Erasing can be performed on the entire memory array,separate blocks, or another unit of the storage elements which is aportion of the memory device. Electrons are transferred from thefloating gates of the storage elements to the p-well region so that theV_(TH) of the storage elements becomes negative.

In the read and verify operations, the select gates (SGD and SGS) areconnected to a voltage in a range of 2.5 to 4.5 V and the unselectedword lines (e.g., WL0, WL1 and WL3, when WL2 is the selected word line)are raised to a read pass voltage, V_(READ), (typically a voltage in therange of 4.5 to 6 V) to make the transistors operate as pass gates. Theselected word line WL2 is connected to a voltage, a level of which isspecified for each read and verify operation in order to determinewhether a V_(TH) of the concerned storage element is above or below suchlevel. For example, in a read operation for a two-level storage element,the selected word line WL2 may be grounded, so that it is detectedwhether the V_(TH) is higher than 0 V. In a verify operation for a twolevel storage element, the selected word line WL2 is connected to 0.8 V,for example, so that it is verified whether or not the V_(TH) hasreached at least 0.8 V. The source and p-well are at 0 V. The selectedbit lines, assumed to be the even bit lines (BLe), are pre-charged to alevel of, for example, 0.7 V. If the V_(TH) is higher than the read orverify level on the word line, the potential level of the bit line (BLe)associated with the storage element of interest maintains the high levelbecause of the non-conductive storage element. On the other hand, if theV_(TH) is lower than the read or verify level, the potential level ofthe concerned bit line (BLe) decreases to a low level, for example, lessthan 0.5 V, because the conductive storage element discharges the bitline. The state of the storage element can thereby be detected by avoltage comparator sense amplifier that is connected to the bit line.

The erase, read and verify operations described above are performedaccording to techniques known in the art. Thus, many of the detailsexplained can be varied by one skilled in the art. Other erase, read andverify techniques known in the art can also be used.

FIG. 23 depicts an example set of threshold voltage distributions.Example V_(TH) distributions for the storage element array are providedfor a case where each storage element stores two bits of data. A firstthreshold voltage distribution E is provided for erased storageelements. Three threshold voltage distributions, A, B and C forprogrammed storage elements, are also depicted. In one embodiment, thethreshold voltages in the E distribution are negative and the thresholdvoltages in the A, B and C distributions are positive.

Each distinct threshold voltage range corresponds to predeterminedvalues for the set of data bits. The specific relationship between thedata programmed into the storage element and the threshold voltagelevels of the storage element depends upon the data encoding schemeadopted for the storage elements. For example, U.S. Pat. No. 6,222,762and U.S. Patent Application Publication No. 2004/0255090, published Dec.16, 2004 (issued as U.S. Pat. No. 7,237,074 on Jun. 26, 2007), each ofwhich are incorporated herein by reference in their entirety, describevarious data encoding schemes for multi-state flash storage elements. Inone embodiment, data values are assigned to the threshold voltage rangesusing a Gray code assignment so that if the threshold voltage of afloating gate erroneously shifts to its neighboring physical state, onlyone bit will be affected. One example assigns “11” to threshold voltagerange E (state E), “10” to threshold voltage range A (state A), “00” tothreshold voltage range B (state B) and “01” to threshold voltage rangeC (state C). However, in other embodiments, Gray code is not used.Although four states are shown, the present invention can also be usedwith other multi-state structures including those that include more orless than four states.

Three read reference voltages, Vra, Vrb and Vrc, are also provided forreading data from storage elements. By testing whether the thresholdvoltage of a given storage element is above or below Vra, Vrb and Vrc,the system can determine the state, e.g., programming condition, thestorage element is in.

Further, three verify reference voltages, Vva, Vvb and Vvc, areprovided. When programming storage elements to state A, the system willtest whether those storage elements have a threshold voltage greaterthan or equal to Vva. When programming storage elements to state B, thesystem will test whether the storage elements have threshold voltagesgreater than or equal to Vvb. When programming storage elements to stateC, the system will determine whether storage elements have theirthreshold voltage greater than or equal to Vvc.

In one embodiment, known as full sequence programming, storage elementscan be programmed from the erase state E directly to any of theprogrammed states A, B or C. For example, a population of storageelements to be programmed may first be erased so that all storageelements in the population are in erased state E. A series ofprogramming pulses such as depicted by the pulse train of FIG. 27 willthen be used to program storage elements directly into states A, B or C.While some storage elements are being programmed from state E to stateA, other storage elements are being programmed from state E to state Band/or from state E to state C. When programming from state E to state Con WLn, the amount of parasitic coupling to the adjacent floating gateunder WLn−1 is a maximized since the change in amount of charge on thefloating gate under WLn is largest as compared to the change in voltagewhen programming from state E to state A or state E to state B. Whenprogramming from state E to state B the amount of coupling to theadjacent floating gate is reduced but still significant. Whenprogramming from state E to state A the amount of coupling is reducedeven further. Consequently the amount of correction required tosubsequently read each state of WLn−1 will vary depending on the stateof the adjacent storage element on WLn.

FIG. 24 depicts an example of a two-pass technique of programming amulti-state storage element that stores data for two different pages: alower page and an upper page. Four states are depicted: state E (11),state A (10), state B (00) and state C (01). For state E, both pagesstore a “1.” For state A, the lower page stores a “0” and the upper pagestores a “1.” For state B, both pages store “0.” For state C, the lowerpage stores “1” and the upper page stores “0.” Note that althoughspecific bit patterns have been assigned to each of the states,different bit patterns may also be assigned.

In a first programming pass, the storage element's threshold voltagelevel is set according to the bit to be programmed into the lowerlogical page. If that bit is a logic “1,” the threshold voltage is notchanged since it is in the appropriate state as a result of having beenearlier erased. However, if the bit to be programmed is a logic “0,” thethreshold level of the storage element is increased to be state A, asshown by arrow 2400. That concludes the first programming pass.

In a second programming pass, the storage element's threshold voltagelevel is set according to the bit being programmed into the upperlogical page. If the upper logical page bit is to store a logic “1,”then no programming occurs since the storage element is in one of thestates E or A, depending upon the programming of the lower page bit,both of which carry an upper page bit of “1.” If the upper page bit isto be a logic “0,” then the threshold voltage is shifted. If the firstpass resulted in the storage element remaining in the erased state E,then in the second phase the storage element is programmed so that thethreshold voltage is increased to be within state C, as depicted byarrow 2420. If the storage element had been programmed into state A as aresult of the first programming pass, then the storage element isfurther programmed in the second pass so that the threshold voltage isincreased to be within state B, as depicted by arrow 2410. The result ofthe second pass is to program the storage element into the statedesignated to store a logic “0” for the upper page without changing thedata for the lower page. In both FIG. 23 and FIG. 24 the amount ofcoupling to the floating gate on the adjacent word line depends on thefinal state.

In one embodiment, a system can be set up to perform full sequencewriting if enough data is written to fill up an entire page. If notenough data is written for a full page, then the programming process canprogram the lower page programming with the data received. Whensubsequent data is received, the system will then program the upperpage. In yet another embodiment, the system can start writing in themode that programs the lower page and convert to full sequenceprogramming mode if enough data is subsequently received to fill up anentire (or most of a) word line's storage elements. More details of suchan embodiment are disclosed in U.S. Patent Application Pub. No.2006/0126390, titled “Pipelined Programming of Non-Volatile MemoriesUsing Early Data,” published Jun. 15, 2006 (issued as U.S. Pat. No.7,120,051 on Oct. 10, 2006), incorporated herein by reference in itsentirety.

FIGS. 25a-c disclose another process for programming non-volatile memorythat reduces the effect of floating gate to floating gate coupling by,for any particular storage element, writing to that particular storageelement with respect to a particular page subsequent to writing toadjacent storage elements for previous pages. In one exampleimplementation, the non-volatile storage elements store two bits of dataper storage element, using four data states. For example, assume thatstate E is the erased state and states A, B and C are the programmedstates. State E stores data 11. State A stores data 01. State B storesdata 10. State C stores data 00. This is an example of non-Gray codingbecause both bits change between adjacent states A and B. Otherencodings of data to physical data states can also be used. Each storageelement stores two pages of data. For reference purposes, these pages ofdata will be called upper page and lower page; however, they can begiven other labels. With reference to state A, the upper page stores bit0 and the lower page stores bit 1. With reference to state B, the upperpage stores bit 1 and the lower page stores bit 0. With reference tostate C, both pages store bit data 0.

The programming process is a two-step process. In the first step, thelower page is programmed. If the lower page is to remain data 1, thenthe storage element state remains at state E. If the data is to beprogrammed to 0, then the threshold of voltage of the storage element israised such that the storage element is programmed to state B′. FIG. 25atherefore shows the programming of storage elements from state E tostate B′. State B′ is an interim state B; therefore, the verify point isdepicted as Vvb′, which is lower than Vvb.

In one embodiment, after a storage element is programmed from state E tostate B′, its neighbor storage element (WLn+1) in the NAND string willthen be programmed with respect to its lower page. For example, lookingback at FIG. 2, after the lower page for storage element 106 isprogrammed, the lower page for storage element 104 would be programmed.After programming storage element 104, the floating gate to floatinggate coupling effect will raise the apparent threshold voltage ofstorage element 106 if storage element 104 had a threshold voltageraised from state E to state B′. This will have the effect of wideningthe threshold voltage distribution for state B′ to that depicted asthreshold voltage distribution 2550 of FIG. 25b. This apparent wideningof the threshold voltage distribution will be remedied when programmingthe upper page.

FIG. 25c depicts the process of programming the upper page. If thestorage element is in erased state E and the upper page is to remain at1, then the storage element will remain in state E. If the storageelement is in state E and its upper page data is to be programmed to 0,then the threshold voltage of the storage element will be raised so thatthe storage element is in state A. If the storage element was inintermediate threshold voltage distribution 2560, which is widenedrelative to distribution 2550, and the upper page data is to remain at1, then the storage element will be programmed to final state B. If thestorage element is in intermediate threshold voltage distribution 2560and the upper page data is to become data 0, then the threshold voltageof the storage element will be raised so that the storage element is instate C. The process depicted by FIGS. 25a-c reduces the effect offloating gate to floating gate coupling because only the upper pageprogramming of neighbor storage elements will have an effect on theapparent threshold voltage of a given storage element. An example of analternate state coding is to move from distribution 2560 to state C whenthe upper page data is a 1, and to move to state B when the upper pagedata is a 0.

Although FIGS. 25a-c provide an example with respect to four data statesand two pages of data, the concepts taught can be applied to otherimplementations with more or fewer than four states and different thantwo pages.

FIG. 26 is a flow chart describing one embodiment of a method forprogramming non-volatile memory. In one implementation, storage elementsare erased (in blocks or other units) prior to programming. In step2600, a body bias is applied, as discussed previously. In step 2602, a“data load” command is issued by the controller and input received bycontrol circuitry 1910. In step 2605, address data designating the pageaddress is input to decoder 1914 from the controller or host. In step2610, a page of program data for the addressed page is input to a databuffer for programming. That data is latched in the appropriate set oflatches. In step 2615, a “program” command is issued by the controllerto state machine 1912.

Triggered by the “program” command, the data latched in step 2610 willbe programmed into the selected storage elements controlled by statemachine 1912 using the stepped program pulses 2705, 2710, 2715, 2720,2725, 2730, 2735, 2740, 2745, 2750, . . . of the pulse train 2700 ofFIG. 27 applied to the appropriate selected word line. In step 2620, theprogram voltage, V_(PGM), is initialized to the starting pulse (e.g., 12V or other value) and a program counter (PC) maintained by state machine1912 is initialized at zero. In step 2630, the first V_(PGM) pulse isapplied to the selected word line to begin programming storage elementsassociated with the selected word line. If logic “0” is stored in aparticular data latch indicating that the corresponding storage elementshould be programmed, then the corresponding bit line is grounded. Onthe other hand, if logic “1” is stored in the particular latchindicating that the corresponding storage element should remain in itscurrent data state, then the corresponding bit line is connected to Vddto inhibit programming.

In step 2635, the states of the selected storage elements are verified.If it is detected that the target threshold voltage of a selectedstorage element has reached the appropriate level, then the data storedin the corresponding data latch is changed to a logic “1.” If it isdetected that the threshold voltage has not reached the appropriatelevel, the data stored in the corresponding data latch is not changed.In this manner, a bit line having a logic “1” stored in itscorresponding data latch does not need to be programmed. When all of thedata latches are storing logic “1,” the state machine (via the wired-ORtype mechanism described above) knows that all selected storage elementshave been programmed. In step 2640, a check is made as to whether all ofthe data latches are storing logic “1.” If all of the data latches arestoring logic “1,” the programming process is complete and successfulbecause all selected storage elements were programmed and verified. Astatus of “PASS” is reported in step 2645.

If, in step 2640, it is determined that not all of the data latches arestoring logic “1,” then the programming process continues. In step 2650,the program counter PC is checked against a program limit value PCmax.One example of a program limit value is twenty; however, other numberscan also be used. If the program counter PC is not less than PCmax, thenthe program process has failed and a status of “FAIL” is reported instep 2655. If the program counter PC is less than PCmax, then V_(PGM) isincreased by the step size and the program counter PC is incremented instep 2660. The process loops back to step 2630 to apply the next V_(PGM)pulse.

In some situations, as discussed, the body bias level can be variedduring programming. For example, a body bias which is set based on aselected word line position can be varied as the selected word linechanges during programming.

FIG. 27 depicts an example pulse train 2700 applied to the control gatesof non-volatile storage elements during programming. The pulse train2700 includes a series of program pulses 2705, 2710, 2715, 2720, 2725,2730, 2735, 2740, 2745, 2750, . . . , that are applied to a word lineselected for programming. In one embodiment, the programming pulses havea voltage, V_(PGM), which starts at 12 V and increases by increments,e.g., 0.5 V, for each successive programming pulse until a maximum of 20V is reached. In between the program pulses are verify pulses. Forexample, verify pulse set 2706 includes three verify pulses. In someembodiments, there can be a verify pulse for each state that data isbeing programmed into, e.g., state A, B and C. In other embodiments,there can be more or fewer verify pulses. The verify pulses in each setcan have amplitudes of Vva, Vvb and Vvc (FIG. 24) or Vvb′ (FIG. 25a),for instance.

The foregoing detailed description of the invention has been presentedfor purposes of illustration and description. It is not intended to beexhaustive or to limit the invention to the precise form disclosed. Manymodifications and variations are possible in light of the aboveteaching. The described embodiments were chosen in order to best explainthe principles of the invention and its practical application, tothereby enable others skilled in the art to best utilize the inventionin various embodiments and with various modifications as are suited tothe particular use contemplated. It is intended that the scope of theinvention be defined by the claims appended hereto.

What is claimed is:
 1. A method for operating non-volatile storage,comprising, during a first time interval: performing operations on afirst set of NAND strings; biasing the first set of NAND strings bycontrolling a first voltage provided to a source side of the first setof NAND strings via a first source voltage supply line and a secondvoltage provided to a p-well region on which the first set of NANDstrings are formed, at least in part; and floating a source side of asecond set of NAND strings which are formed, at least in part, on thep-well region by floating a second source voltage supply line for thesecond set of NAND strings, wherein operations comprising at least oneof reading operations and or verifying operations, are not performed onthe second set of NAND strings during the first time interval, whereinthe first voltage is applied to the first source voltage supply line ata same time as the second source voltage supply line is floated.
 2. Themethod of claim 1, wherein: the first voltage is provided via a firstsource voltage supply line.
 3. The method of claim 1, wherein: thefloating the source side of the second set of NAND strings comprisesfloating a second source voltage supply line for the second set of NANDstrings.
 4. The method of claim 1, wherein: a difference between thefirst and second voltages is based on a desired bias level.
 5. Themethod of claim 1, wherein: the operations performed on the first set ofNAND strings comprise at least one of reading operations and orverifying operations.
 6. The method of claim 1, further comprising,during a second time interval outside the first time interval:performing operations on the second set of NAND strings; biasing thesecond set of NAND strings by controlling a voltage provided to thesource side of the second set of NAND strings and a voltage provided tothe p-well region; and floating the source side of the first set of NANDstrings, where operations comprising at least one of reading operationsand or verifying operations, are not performed on the first set of NANDstrings during the second time interval.
 7. A non-volatile storagesystem, comprising: first and second sets of NAND strings formed, atleast in part, on a p-well region of a substrate; and one or morecontrol circuits in communication with the first and second sets of NANDstrings, the one or more control circuits, during a first time interval:(a) perform operations on the first set of NAND strings, (b) bias thefirst set of NAND strings by controlling a first voltage provided to asource side of the first set of NAND strings via a first source voltagesupply line and a second voltage provided to the p-well region, and (c)floating float a source side of the second set of NAND strings byfloating a second source voltage supply line for the second set of NANDstrings, wherein the first voltage is provided to the first sourcevoltage supply line at a same time as the second source voltage supplyline is floated, and during a second time interval outside the firsttime interval, the one or more control circuits: (d) perform operationson the second set of NAND strings, (e) bias the second set of NANDstrings by controlling a voltage provided to the source side of thesecond set of NAND strings via the second source voltage supply line anda voltage provided to the p-well region, and (f) float the source sideof the first set of NAND strings by floating the first source voltagesupply line, where wherein the second voltage is provided to the secondsource voltage supply line at a same time as the first source voltagesupply line is floated, and operations comprising at least one ofreading operations and or verifying operations are not performed on thefirst set of NAND strings during the second time interval.
 8. Thenon-volatile storage system of claim 7, wherein: operations comprisingat least one of reading operations and or verifying operations, are notperformed on the second set of NAND strings during the first timeinterval.
 9. The non-volatile storage system of claim 7, wherein: thefirst voltage is provided via a first source voltage supply line. 10.The non-volatile storage system of claim 7, wherein: the one or morecontrol circuits float the source side of the second set of NAND stringsby floating a second source voltage supply line for the second set ofNAND strings.
 11. The non-volatile storage system of claim 7, wherein: adifference between the first and second voltages is based on a desiredbias level.
 12. The non-volatile storage system of claim 7, wherein: theoperations performed on the first set of NAND strings comprise at leastone of reading operations and or verifying operations.
 13. The method ofclaim 1, wherein: the first and second sets of NAND strings comprisesstorage elements in a three-dimensional array of storage elements. 14.The non-volatile storage system of claim 7, wherein: the first andsecond sets of NAND strings comprises storage elements in athree-dimensional array of storage elements.